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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_gpio_ps___config.html">XGpioPs_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for a device.  <a href="struct_x_gpio_ps___config.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> driver instance data.  <a href="struct_x_gpio_ps.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga1e440e05bbea534ebf6939e88eb1455f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga1e440e05bbea534ebf6939e88eb1455f">XGPIOPS_BANK_MAX_PINS</a>&#160;&#160;&#160;(u32)32</td></tr>
<tr class="memdesc:ga1e440e05bbea534ebf6939e88eb1455f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max pins in a GPIO bank.  <a href="#ga1e440e05bbea534ebf6939e88eb1455f">More...</a><br /></td></tr>
<tr class="separator:ga1e440e05bbea534ebf6939e88eb1455f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac5c6fe277747f034cd30c3f3e770dc5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gac5c6fe277747f034cd30c3f3e770dc5b">XGPIOPS_BANK0</a>&#160;&#160;&#160;0x00U</td></tr>
<tr class="memdesc:gac5c6fe277747f034cd30c3f3e770dc5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">GPIO Bank 0.  <a href="#gac5c6fe277747f034cd30c3f3e770dc5b">More...</a><br /></td></tr>
<tr class="separator:gac5c6fe277747f034cd30c3f3e770dc5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga88ebd56b0defc49ebd308951df1eaf0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga88ebd56b0defc49ebd308951df1eaf0e">XGPIOPS_BANK1</a>&#160;&#160;&#160;0x01U</td></tr>
<tr class="memdesc:ga88ebd56b0defc49ebd308951df1eaf0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">GPIO Bank 1.  <a href="#ga88ebd56b0defc49ebd308951df1eaf0e">More...</a><br /></td></tr>
<tr class="separator:ga88ebd56b0defc49ebd308951df1eaf0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae57e0fee992d409f0ff32d35e68f6fbc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gae57e0fee992d409f0ff32d35e68f6fbc">XGPIOPS_BANK2</a>&#160;&#160;&#160;0x02U</td></tr>
<tr class="memdesc:gae57e0fee992d409f0ff32d35e68f6fbc"><td class="mdescLeft">&#160;</td><td class="mdescRight">GPIO Bank 2.  <a href="#gae57e0fee992d409f0ff32d35e68f6fbc">More...</a><br /></td></tr>
<tr class="separator:gae57e0fee992d409f0ff32d35e68f6fbc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac994de03aa64e2b6b3c6b6da9d76e020"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gac994de03aa64e2b6b3c6b6da9d76e020">XGPIOPS_BANK3</a>&#160;&#160;&#160;0x03U</td></tr>
<tr class="memdesc:gac994de03aa64e2b6b3c6b6da9d76e020"><td class="mdescLeft">&#160;</td><td class="mdescRight">GPIO Bank 3.  <a href="#gac994de03aa64e2b6b3c6b6da9d76e020">More...</a><br /></td></tr>
<tr class="separator:gac994de03aa64e2b6b3c6b6da9d76e020"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8661a0444fd67d2b87a14b3c196e571"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gab8661a0444fd67d2b87a14b3c196e571">XGPIOPS_MAX_BANKS_ZYNQMP</a>&#160;&#160;&#160;0x06U</td></tr>
<tr class="memdesc:gab8661a0444fd67d2b87a14b3c196e571"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max banks in a Zynq Ultrascale+ MP GPIO device.  <a href="#gab8661a0444fd67d2b87a14b3c196e571">More...</a><br /></td></tr>
<tr class="separator:gab8661a0444fd67d2b87a14b3c196e571"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga27b466ba78cf142027ca998d0d67d2e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga27b466ba78cf142027ca998d0d67d2e0">XGPIOPS_MAX_BANKS</a>&#160;&#160;&#160;0x04U</td></tr>
<tr class="memdesc:ga27b466ba78cf142027ca998d0d67d2e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max banks in a Zynq GPIO device.  <a href="#ga27b466ba78cf142027ca998d0d67d2e0">More...</a><br /></td></tr>
<tr class="separator:ga27b466ba78cf142027ca998d0d67d2e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8f80173cb28cbac5bab53c4fc7c7dd96"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga8f80173cb28cbac5bab53c4fc7c7dd96">XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP</a>&#160;&#160;&#160;(u32)174</td></tr>
<tr class="memdesc:ga8f80173cb28cbac5bab53c4fc7c7dd96"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max pins in the Zynq Ultrascale+ MP GPIO device 0 - 25, Bank 0 26 - 51, Bank 1 52 - 77, Bank 2 78 - 109, Bank 3 110 - 141, Bank 4 142 - 173, Bank 5.  <a href="#ga8f80173cb28cbac5bab53c4fc7c7dd96">More...</a><br /></td></tr>
<tr class="separator:ga8f80173cb28cbac5bab53c4fc7c7dd96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d70822b76e1dd3fda458ed693a082af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga6d70822b76e1dd3fda458ed693a082af">XGPIOPS_DEVICE_MAX_PIN_NUM</a>&#160;&#160;&#160;(u32)118</td></tr>
<tr class="memdesc:ga6d70822b76e1dd3fda458ed693a082af"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max pins in the Zynq GPIO device 0 - 31, Bank 0 32 - 53, Bank 1 54 - 85, Bank 2 86 - 117, Bank 3.  <a href="#ga6d70822b76e1dd3fda458ed693a082af">More...</a><br /></td></tr>
<tr class="separator:ga6d70822b76e1dd3fda458ed693a082af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaff08ac5be0729f046324cae2706aaf9a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gaff08ac5be0729f046324cae2706aaf9a">XGpioPs_ReadReg</a>(BaseAddr,  RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddr) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:gaff08ac5be0729f046324cae2706aaf9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the given register.  <a href="#gaff08ac5be0729f046324cae2706aaf9a">More...</a><br /></td></tr>
<tr class="separator:gaff08ac5be0729f046324cae2706aaf9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3ad586332c0958c5044450d735127337"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga3ad586332c0958c5044450d735127337">XGpioPs_WriteReg</a>(BaseAddr,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:ga3ad586332c0958c5044450d735127337"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes to the given register.  <a href="#ga3ad586332c0958c5044450d735127337">More...</a><br /></td></tr>
<tr class="separator:ga3ad586332c0958c5044450d735127337"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:ga85028e3aa9d71291581c0c7036f6c2d9"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga85028e3aa9d71291581c0c7036f6c2d9">XGpioPs_Handler</a>) (void *CallBackRef, u32 Bank, u32 Status)</td></tr>
<tr class="memdesc:ga85028e3aa9d71291581c0c7036f6c2d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This handler data type allows the user to define a callback function to handle the interrupts for the GPIO device.  <a href="#ga85028e3aa9d71291581c0c7036f6c2d9">More...</a><br /></td></tr>
<tr class="separator:ga85028e3aa9d71291581c0c7036f6c2d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga33d678e910c69c63487773ca55abff47"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga33d678e910c69c63487773ca55abff47">StubHandler</a> (void *CallBackRef, u32 Bank, u32 Status)</td></tr>
<tr class="memdesc:ga33d678e910c69c63487773ca55abff47"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is a stub for the status callback.  <a href="#ga33d678e910c69c63487773ca55abff47">More...</a><br /></td></tr>
<tr class="separator:ga33d678e910c69c63487773ca55abff47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e7bc106ec7c6108c26dfe835713d501"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga8e7bc106ec7c6108c26dfe835713d501">XGpioPs_Read</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank)</td></tr>
<tr class="memdesc:ga8e7bc106ec7c6108c26dfe835713d501"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the Data register of the specified GPIO bank.  <a href="#ga8e7bc106ec7c6108c26dfe835713d501">More...</a><br /></td></tr>
<tr class="separator:ga8e7bc106ec7c6108c26dfe835713d501"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga13b3e68acd59636ebaed5c71055e583c"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga13b3e68acd59636ebaed5c71055e583c">XGpioPs_ReadPin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin)</td></tr>
<tr class="memdesc:ga13b3e68acd59636ebaed5c71055e583c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Data from the specified pin.  <a href="#ga13b3e68acd59636ebaed5c71055e583c">More...</a><br /></td></tr>
<tr class="separator:ga13b3e68acd59636ebaed5c71055e583c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacda78d38a3b2dbf4398c5df2c88e0424"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gacda78d38a3b2dbf4398c5df2c88e0424">XGpioPs_Write</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank, u32 Data)</td></tr>
<tr class="memdesc:gacda78d38a3b2dbf4398c5df2c88e0424"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to the Data register of the specified GPIO bank.  <a href="#gacda78d38a3b2dbf4398c5df2c88e0424">More...</a><br /></td></tr>
<tr class="separator:gacda78d38a3b2dbf4398c5df2c88e0424"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4f1789ef303dcbfbdb402663e7b0019d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga4f1789ef303dcbfbdb402663e7b0019d">XGpioPs_WritePin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin, u32 Data)</td></tr>
<tr class="memdesc:ga4f1789ef303dcbfbdb402663e7b0019d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write data to the specified pin.  <a href="#ga4f1789ef303dcbfbdb402663e7b0019d">More...</a><br /></td></tr>
<tr class="separator:ga4f1789ef303dcbfbdb402663e7b0019d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga85638e14681720794efa7e55d69360fc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga85638e14681720794efa7e55d69360fc">XGpioPs_SetDirection</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank, u32 Direction)</td></tr>
<tr class="memdesc:ga85638e14681720794efa7e55d69360fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the Direction of the pins of the specified GPIO Bank.  <a href="#ga85638e14681720794efa7e55d69360fc">More...</a><br /></td></tr>
<tr class="separator:ga85638e14681720794efa7e55d69360fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2dc5d53b864a3beb90481390f06e1099"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga2dc5d53b864a3beb90481390f06e1099">XGpioPs_SetDirectionPin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin, u32 Direction)</td></tr>
<tr class="memdesc:ga2dc5d53b864a3beb90481390f06e1099"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the Direction of the specified pin.  <a href="#ga2dc5d53b864a3beb90481390f06e1099">More...</a><br /></td></tr>
<tr class="separator:ga2dc5d53b864a3beb90481390f06e1099"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga158c9afe847d2b5f6bab24d20926c359"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga158c9afe847d2b5f6bab24d20926c359">XGpioPs_GetDirection</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank)</td></tr>
<tr class="memdesc:ga158c9afe847d2b5f6bab24d20926c359"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the Direction of the pins of the specified GPIO Bank.  <a href="#ga158c9afe847d2b5f6bab24d20926c359">More...</a><br /></td></tr>
<tr class="separator:ga158c9afe847d2b5f6bab24d20926c359"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga07a1af7cd9070c4037773cc30d53c364"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga07a1af7cd9070c4037773cc30d53c364">XGpioPs_GetDirectionPin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin)</td></tr>
<tr class="memdesc:ga07a1af7cd9070c4037773cc30d53c364"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the Direction of the specified pin.  <a href="#ga07a1af7cd9070c4037773cc30d53c364">More...</a><br /></td></tr>
<tr class="separator:ga07a1af7cd9070c4037773cc30d53c364"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga867a6006d591516ed79727bb6392b9ac"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga867a6006d591516ed79727bb6392b9ac">XGpioPs_SetOutputEnable</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank, u32 OpEnable)</td></tr>
<tr class="memdesc:ga867a6006d591516ed79727bb6392b9ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the Output Enable of the pins of the specified GPIO Bank.  <a href="#ga867a6006d591516ed79727bb6392b9ac">More...</a><br /></td></tr>
<tr class="separator:ga867a6006d591516ed79727bb6392b9ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae84916ec202e4d3a8a46a20857753eec"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gae84916ec202e4d3a8a46a20857753eec">XGpioPs_SetOutputEnablePin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin, u32 OpEnable)</td></tr>
<tr class="memdesc:gae84916ec202e4d3a8a46a20857753eec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the Output Enable of the specified pin.  <a href="#gae84916ec202e4d3a8a46a20857753eec">More...</a><br /></td></tr>
<tr class="separator:gae84916ec202e4d3a8a46a20857753eec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac182a9828e0ecfdc7a1cbe0c5a1a763f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gac182a9828e0ecfdc7a1cbe0c5a1a763f">XGpioPs_GetOutputEnable</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank)</td></tr>
<tr class="memdesc:gac182a9828e0ecfdc7a1cbe0c5a1a763f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the Output Enable status of the pins of the specified GPIO Bank.  <a href="#gac182a9828e0ecfdc7a1cbe0c5a1a763f">More...</a><br /></td></tr>
<tr class="separator:gac182a9828e0ecfdc7a1cbe0c5a1a763f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d3c0e39d48cd827e3e10be5429f5b30"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga5d3c0e39d48cd827e3e10be5429f5b30">XGpioPs_GetOutputEnablePin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin)</td></tr>
<tr class="memdesc:ga5d3c0e39d48cd827e3e10be5429f5b30"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the Output Enable status of the specified pin.  <a href="#ga5d3c0e39d48cd827e3e10be5429f5b30">More...</a><br /></td></tr>
<tr class="separator:ga5d3c0e39d48cd827e3e10be5429f5b30"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga173133193aeba362fa0a5c6e7cdd8dfa"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga173133193aeba362fa0a5c6e7cdd8dfa">XGpioPs_SelfTest</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga173133193aeba362fa0a5c6e7cdd8dfa"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function runs a self-test on the GPIO driver/device.  <a href="#ga173133193aeba362fa0a5c6e7cdd8dfa">More...</a><br /></td></tr>
<tr class="separator:ga173133193aeba362fa0a5c6e7cdd8dfa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga812e5a4df20dcae1a95ec4b15d36f039"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga812e5a4df20dcae1a95ec4b15d36f039">XGpioPs_IntrEnable</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank, u32 Mask)</td></tr>
<tr class="memdesc:ga812e5a4df20dcae1a95ec4b15d36f039"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the interrupts for the specified pins in the specified bank.  <a href="#ga812e5a4df20dcae1a95ec4b15d36f039">More...</a><br /></td></tr>
<tr class="separator:ga812e5a4df20dcae1a95ec4b15d36f039"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b84f2cbaaa08abf138209b975192326"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga5b84f2cbaaa08abf138209b975192326">XGpioPs_IntrDisable</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank, u32 Mask)</td></tr>
<tr class="memdesc:ga5b84f2cbaaa08abf138209b975192326"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function disables the interrupts for the specified pins in the specified bank.  <a href="#ga5b84f2cbaaa08abf138209b975192326">More...</a><br /></td></tr>
<tr class="separator:ga5b84f2cbaaa08abf138209b975192326"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaff7a79032f9e298f73c48763e7723bfd"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gaff7a79032f9e298f73c48763e7723bfd">XGpioPs_IntrGetEnabled</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank)</td></tr>
<tr class="memdesc:gaff7a79032f9e298f73c48763e7723bfd"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the interrupt enable status for a bank.  <a href="#gaff7a79032f9e298f73c48763e7723bfd">More...</a><br /></td></tr>
<tr class="separator:gaff7a79032f9e298f73c48763e7723bfd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga029493370cece06799abb021207cf53f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga029493370cece06799abb021207cf53f">XGpioPs_IntrGetStatus</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank)</td></tr>
<tr class="memdesc:ga029493370cece06799abb021207cf53f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns interrupt status read from Interrupt Status Register.  <a href="#ga029493370cece06799abb021207cf53f">More...</a><br /></td></tr>
<tr class="separator:ga029493370cece06799abb021207cf53f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1168915d3d7b4803bcf30799e0bfdc32"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga1168915d3d7b4803bcf30799e0bfdc32">XGpioPs_IntrClear</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank, u32 Mask)</td></tr>
<tr class="memdesc:ga1168915d3d7b4803bcf30799e0bfdc32"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears pending interrupt(s) with the provided mask.  <a href="#ga1168915d3d7b4803bcf30799e0bfdc32">More...</a><br /></td></tr>
<tr class="separator:ga1168915d3d7b4803bcf30799e0bfdc32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga47789beb1dcd80b9ef68adaa9eb6b6bf"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga47789beb1dcd80b9ef68adaa9eb6b6bf">XGpioPs_SetIntrType</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank, u32 IntrType, u32 IntrPolarity, u32 IntrOnAny)</td></tr>
<tr class="memdesc:ga47789beb1dcd80b9ef68adaa9eb6b6bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used for setting the Interrupt Type, Interrupt Polarity and Interrupt On Any for the specified GPIO Bank pins.  <a href="#ga47789beb1dcd80b9ef68adaa9eb6b6bf">More...</a><br /></td></tr>
<tr class="separator:ga47789beb1dcd80b9ef68adaa9eb6b6bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad1e07837d6bfe1cf16d0b8a454a7de29"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gad1e07837d6bfe1cf16d0b8a454a7de29">XGpioPs_GetIntrType</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u8 Bank, u32 *IntrType, u32 *IntrPolarity, u32 *IntrOnAny)</td></tr>
<tr class="memdesc:gad1e07837d6bfe1cf16d0b8a454a7de29"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used for getting the Interrupt Type, Interrupt Polarity and Interrupt On Any for the specified GPIO Bank pins.  <a href="#gad1e07837d6bfe1cf16d0b8a454a7de29">More...</a><br /></td></tr>
<tr class="separator:gad1e07837d6bfe1cf16d0b8a454a7de29"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd63e0e5c7ed18517d54104e4ad6dcd4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gacd63e0e5c7ed18517d54104e4ad6dcd4">XGpioPs_SetCallbackHandler</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, void *CallBackRef, <a class="el" href="group__gpiops__v3__1.html#ga85028e3aa9d71291581c0c7036f6c2d9">XGpioPs_Handler</a> FuncPointer)</td></tr>
<tr class="memdesc:gacd63e0e5c7ed18517d54104e4ad6dcd4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the status callback function.  <a href="#gacd63e0e5c7ed18517d54104e4ad6dcd4">More...</a><br /></td></tr>
<tr class="separator:gacd63e0e5c7ed18517d54104e4ad6dcd4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca8012790789d80573f4b2fa9e601e7c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gaca8012790789d80573f4b2fa9e601e7c">XGpioPs_IntrHandler</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaca8012790789d80573f4b2fa9e601e7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the interrupt handler for GPIO interrupts.It checks the interrupt status registers of all the banks to determine the actual bank in which an interrupt has been triggered.  <a href="#gaca8012790789d80573f4b2fa9e601e7c">More...</a><br /></td></tr>
<tr class="separator:gaca8012790789d80573f4b2fa9e601e7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga963415d9096b5887c5388cea74cd1116"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga963415d9096b5887c5388cea74cd1116">XGpioPs_SetIntrTypePin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin, u8 IrqType)</td></tr>
<tr class="memdesc:ga963415d9096b5887c5388cea74cd1116"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used for setting the IRQ Type of a single GPIO pin.  <a href="#ga963415d9096b5887c5388cea74cd1116">More...</a><br /></td></tr>
<tr class="separator:ga963415d9096b5887c5388cea74cd1116"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d91233cc0556e3eb8d39cc856b6436c"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga1d91233cc0556e3eb8d39cc856b6436c">XGpioPs_GetIntrTypePin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin)</td></tr>
<tr class="memdesc:ga1d91233cc0556e3eb8d39cc856b6436c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the IRQ Type of a given GPIO pin.  <a href="#ga1d91233cc0556e3eb8d39cc856b6436c">More...</a><br /></td></tr>
<tr class="separator:ga1d91233cc0556e3eb8d39cc856b6436c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc4ea201a1c488a1b667a77f3c6fd23b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gadc4ea201a1c488a1b667a77f3c6fd23b">XGpioPs_IntrEnablePin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin)</td></tr>
<tr class="memdesc:gadc4ea201a1c488a1b667a77f3c6fd23b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the interrupt for the specified pin.  <a href="#gadc4ea201a1c488a1b667a77f3c6fd23b">More...</a><br /></td></tr>
<tr class="separator:gadc4ea201a1c488a1b667a77f3c6fd23b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a00fd131bf76eab2dcdd48079845b37"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga8a00fd131bf76eab2dcdd48079845b37">XGpioPs_IntrDisablePin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin)</td></tr>
<tr class="memdesc:ga8a00fd131bf76eab2dcdd48079845b37"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function disables the interrupts for the specified pin.  <a href="#ga8a00fd131bf76eab2dcdd48079845b37">More...</a><br /></td></tr>
<tr class="separator:ga8a00fd131bf76eab2dcdd48079845b37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga612ecefd5e1f81cccf6b878505b7e242"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga612ecefd5e1f81cccf6b878505b7e242">XGpioPs_IntrGetEnabledPin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin)</td></tr>
<tr class="memdesc:ga612ecefd5e1f81cccf6b878505b7e242"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns whether interrupts are enabled for the specified pin.  <a href="#ga612ecefd5e1f81cccf6b878505b7e242">More...</a><br /></td></tr>
<tr class="separator:ga612ecefd5e1f81cccf6b878505b7e242"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ed8ee94fdf3f26e765a997aeab64595"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga7ed8ee94fdf3f26e765a997aeab64595">XGpioPs_IntrGetStatusPin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin)</td></tr>
<tr class="memdesc:ga7ed8ee94fdf3f26e765a997aeab64595"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns interrupt enable status of the specified pin.  <a href="#ga7ed8ee94fdf3f26e765a997aeab64595">More...</a><br /></td></tr>
<tr class="separator:ga7ed8ee94fdf3f26e765a997aeab64595"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga27216bebe86f0d32540920a40674340f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga27216bebe86f0d32540920a40674340f">XGpioPs_IntrClearPin</a> (<a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *InstancePtr, u32 Pin)</td></tr>
<tr class="memdesc:ga27216bebe86f0d32540920a40674340f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the specified pending interrupt.  <a href="#ga27216bebe86f0d32540920a40674340f">More...</a><br /></td></tr>
<tr class="separator:ga27216bebe86f0d32540920a40674340f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9c49687af4625a0ed49f376d3ff1b045"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_gpio_ps___config.html">XGpioPs_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga9c49687af4625a0ed49f376d3ff1b045">XGpioPs_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:ga9c49687af4625a0ed49f376d3ff1b045"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function looks for the device configuration based on the unique device ID.  <a href="#ga9c49687af4625a0ed49f376d3ff1b045">More...</a><br /></td></tr>
<tr class="separator:ga9c49687af4625a0ed49f376d3ff1b045"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a>
Variables</h2></td></tr>
<tr class="memitem:gadfc4a76613b301ad3af6d2014505e745"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_gpio_ps___config.html">XGpioPs_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gadfc4a76613b301ad3af6d2014505e745">XGpioPs_ConfigTable</a> [XPAR_XGPIOPS_NUM_INSTANCES]</td></tr>
<tr class="memdesc:gadfc4a76613b301ad3af6d2014505e745"><td class="mdescLeft">&#160;</td><td class="mdescRight">This table contains configuration information for each GPIO device in the system.  <a href="#gadfc4a76613b301ad3af6d2014505e745">More...</a><br /></td></tr>
<tr class="separator:gadfc4a76613b301ad3af6d2014505e745"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadfc4a76613b301ad3af6d2014505e745"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_gpio_ps___config.html">XGpioPs_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gadfc4a76613b301ad3af6d2014505e745">XGpioPs_ConfigTable</a> [XPAR_XGPIOPS_NUM_INSTANCES]</td></tr>
<tr class="memdesc:gadfc4a76613b301ad3af6d2014505e745"><td class="mdescLeft">&#160;</td><td class="mdescRight">This table contains configuration information for each GPIO device in the system.  <a href="#gadfc4a76613b301ad3af6d2014505e745">More...</a><br /></td></tr>
<tr class="separator:gadfc4a76613b301ad3af6d2014505e745"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Interrupt types</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp18572496d43f15f681a6844a04f17051"></a>The following constants define the interrupt types that can be set for each GPIO pin. </p>
</td></tr>
<tr class="memitem:ga25b306607f3b370ea355229c21e7db02"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga25b306607f3b370ea355229c21e7db02">XGPIOPS_IRQ_TYPE_EDGE_RISING</a>&#160;&#160;&#160;0x00U</td></tr>
<tr class="memdesc:ga25b306607f3b370ea355229c21e7db02"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt on Rising edge.  <a href="#ga25b306607f3b370ea355229c21e7db02">More...</a><br /></td></tr>
<tr class="separator:ga25b306607f3b370ea355229c21e7db02"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8082ec62bd44c68e3334b77c87fca96"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gae8082ec62bd44c68e3334b77c87fca96">XGPIOPS_IRQ_TYPE_EDGE_FALLING</a>&#160;&#160;&#160;0x01U</td></tr>
<tr class="memdesc:gae8082ec62bd44c68e3334b77c87fca96"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Falling edge.  <a href="#gae8082ec62bd44c68e3334b77c87fca96">More...</a><br /></td></tr>
<tr class="separator:gae8082ec62bd44c68e3334b77c87fca96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaa0415781a99043db06849daa027d5c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#gaaa0415781a99043db06849daa027d5c5">XGPIOPS_IRQ_TYPE_EDGE_BOTH</a>&#160;&#160;&#160;0x02U</td></tr>
<tr class="memdesc:gaaa0415781a99043db06849daa027d5c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt on both edges.  <a href="#gaaa0415781a99043db06849daa027d5c5">More...</a><br /></td></tr>
<tr class="separator:gaaa0415781a99043db06849daa027d5c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga09bf1d6e818f6f442ba61535f8e855ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga09bf1d6e818f6f442ba61535f8e855ea">XGPIOPS_IRQ_TYPE_LEVEL_HIGH</a>&#160;&#160;&#160;0x03U</td></tr>
<tr class="memdesc:ga09bf1d6e818f6f442ba61535f8e855ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt on high level.  <a href="#ga09bf1d6e818f6f442ba61535f8e855ea">More...</a><br /></td></tr>
<tr class="separator:ga09bf1d6e818f6f442ba61535f8e855ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84b599940b75f6e1d6920c7b33fc2789"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpiops__v3__1.html#ga84b599940b75f6e1d6920c7b33fc2789">XGPIOPS_IRQ_TYPE_LEVEL_LOW</a>&#160;&#160;&#160;0x04U</td></tr>
<tr class="memdesc:ga84b599940b75f6e1d6920c7b33fc2789"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt on low level.  <a href="#ga84b599940b75f6e1d6920c7b33fc2789">More...</a><br /></td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Register offsets for the GPIO. Each register is 32 bits.</h2></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_LSW_OFFSET</b>&#160;&#160;&#160;0x00000000U  /* Mask and Data Register LSW, WO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_MSW_OFFSET</b>&#160;&#160;&#160;0x00000004U  /* Mask and Data Register MSW, WO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_OFFSET</b>&#160;&#160;&#160;0x00000040U  /* Data Register, RW */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_RO_OFFSET</b>&#160;&#160;&#160;0x00000060U  /* Data Register - Input, RO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DIRM_OFFSET</b>&#160;&#160;&#160;0x00000204U  /* Direction Mode Register, RW */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_OUTEN_OFFSET</b>&#160;&#160;&#160;0x00000208U  /* Output Enable Register, RW */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTMASK_OFFSET</b>&#160;&#160;&#160;0x0000020CU  /* Interrupt Mask Register, RO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTEN_OFFSET</b>&#160;&#160;&#160;0x00000210U  /* Interrupt Enable Register, WO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTDIS_OFFSET</b>&#160;&#160;&#160;0x00000214U  /* Interrupt Disable Register, WO*/</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTSTS_OFFSET</b>&#160;&#160;&#160;0x00000218U  /* Interrupt Status Register, RO */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_OFFSET</b>&#160;&#160;&#160;0x0000021CU  /* Interrupt Type Register, RW */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTPOL_OFFSET</b>&#160;&#160;&#160;0x00000220U  /* Interrupt Polarity Register, RW */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTANY_OFFSET</b>&#160;&#160;&#160;0x00000224U  /* Interrupt On Any Register, RW */</td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Register offsets for each Bank.</h2></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_MASK_OFFSET</b>&#160;&#160;&#160;0x00000008U  /* Data/Mask Registers offset */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_DATA_BANK_OFFSET</b>&#160;&#160;&#160;0x00000004U  /* Data Registers offset */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_REG_MASK_OFFSET</b>&#160;&#160;&#160;0x00000040U  /* Registers offset */</td></tr>
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Interrupt type reset values for each bank</h2></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK0_RESET</b>&#160;&#160;&#160;0xFFFFFFFFU  /* Resets specific to Zynq */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK1_RESET</b>&#160;&#160;&#160;0x003FFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK2_RESET</b>&#160;&#160;&#160;0xFFFFFFFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK3_RESET</b>&#160;&#160;&#160;0xFFFFFFFFU  /* Reset common to both platforms */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK4_RESET</b>&#160;&#160;&#160;0xFFFFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XGPIOPS_INTTYPE_BANK5_RESET</b>&#160;&#160;&#160;0xFFFFFFFFU</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="gac5c6fe277747f034cd30c3f3e770dc5b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac5c6fe277747f034cd30c3f3e770dc5b">&#9670;&nbsp;</a></span>XGPIOPS_BANK0</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XGPIOPS_BANK0&#160;&#160;&#160;0x00U</td>
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      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>GPIO Bank 0. </p>

<p class="reference">Referenced by <a class="el" href="group__gpiops__v3__1.html#ga173133193aeba362fa0a5c6e7cdd8dfa">XGpioPs_SelfTest()</a>.</p>

</div>
</div>
<a id="ga88ebd56b0defc49ebd308951df1eaf0e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga88ebd56b0defc49ebd308951df1eaf0e">&#9670;&nbsp;</a></span>XGPIOPS_BANK1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XGPIOPS_BANK1&#160;&#160;&#160;0x01U</td>
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      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>GPIO Bank 1. </p>

</div>
</div>
<a id="gae57e0fee992d409f0ff32d35e68f6fbc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae57e0fee992d409f0ff32d35e68f6fbc">&#9670;&nbsp;</a></span>XGPIOPS_BANK2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XGPIOPS_BANK2&#160;&#160;&#160;0x02U</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>GPIO Bank 2. </p>

</div>
</div>
<a id="gac994de03aa64e2b6b3c6b6da9d76e020"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac994de03aa64e2b6b3c6b6da9d76e020">&#9670;&nbsp;</a></span>XGPIOPS_BANK3</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XGPIOPS_BANK3&#160;&#160;&#160;0x03U</td>
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      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>GPIO Bank 3. </p>

</div>
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<a id="ga1e440e05bbea534ebf6939e88eb1455f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1e440e05bbea534ebf6939e88eb1455f">&#9670;&nbsp;</a></span>XGPIOPS_BANK_MAX_PINS</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XGPIOPS_BANK_MAX_PINS&#160;&#160;&#160;(u32)32</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>Max pins in a GPIO bank. </p>

</div>
</div>
<a id="ga6d70822b76e1dd3fda458ed693a082af"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6d70822b76e1dd3fda458ed693a082af">&#9670;&nbsp;</a></span>XGPIOPS_DEVICE_MAX_PIN_NUM</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XGPIOPS_DEVICE_MAX_PIN_NUM&#160;&#160;&#160;(u32)118</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>Max pins in the Zynq GPIO device 0 - 31, Bank 0 32 - 53, Bank 1 54 - 85, Bank 2 86 - 117, Bank 3. </p>

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<a id="ga8f80173cb28cbac5bab53c4fc7c7dd96"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8f80173cb28cbac5bab53c4fc7c7dd96">&#9670;&nbsp;</a></span>XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP&#160;&#160;&#160;(u32)174</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>Max pins in the Zynq Ultrascale+ MP GPIO device 0 - 25, Bank 0 26 - 51, Bank 1 52 - 77, Bank 2 78 - 109, Bank 3 110 - 141, Bank 4 142 - 173, Bank 5. </p>

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<a id="gaaa0415781a99043db06849daa027d5c5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaaa0415781a99043db06849daa027d5c5">&#9670;&nbsp;</a></span>XGPIOPS_IRQ_TYPE_EDGE_BOTH</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XGPIOPS_IRQ_TYPE_EDGE_BOTH&#160;&#160;&#160;0x02U</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>Interrupt on both edges. </p>

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<a id="gae8082ec62bd44c68e3334b77c87fca96"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae8082ec62bd44c68e3334b77c87fca96">&#9670;&nbsp;</a></span>XGPIOPS_IRQ_TYPE_EDGE_FALLING</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define XGPIOPS_IRQ_TYPE_EDGE_FALLING&#160;&#160;&#160;0x01U</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>Interrupt Falling edge. </p>

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<a id="ga25b306607f3b370ea355229c21e7db02"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga25b306607f3b370ea355229c21e7db02">&#9670;&nbsp;</a></span>XGPIOPS_IRQ_TYPE_EDGE_RISING</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XGPIOPS_IRQ_TYPE_EDGE_RISING&#160;&#160;&#160;0x00U</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>Interrupt on Rising edge. </p>

</div>
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<a id="ga09bf1d6e818f6f442ba61535f8e855ea"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga09bf1d6e818f6f442ba61535f8e855ea">&#9670;&nbsp;</a></span>XGPIOPS_IRQ_TYPE_LEVEL_HIGH</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH&#160;&#160;&#160;0x03U</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>Interrupt on high level. </p>

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<a id="ga84b599940b75f6e1d6920c7b33fc2789"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga84b599940b75f6e1d6920c7b33fc2789">&#9670;&nbsp;</a></span>XGPIOPS_IRQ_TYPE_LEVEL_LOW</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XGPIOPS_IRQ_TYPE_LEVEL_LOW&#160;&#160;&#160;0x04U</td>
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</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>Interrupt on low level. </p>

<p class="reference">Referenced by <a class="el" href="group__gpiops__v3__1.html#ga963415d9096b5887c5388cea74cd1116">XGpioPs_SetIntrTypePin()</a>.</p>

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<a id="ga27b466ba78cf142027ca998d0d67d2e0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga27b466ba78cf142027ca998d0d67d2e0">&#9670;&nbsp;</a></span>XGPIOPS_MAX_BANKS</h2>

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          <td class="memname">#define XGPIOPS_MAX_BANKS&#160;&#160;&#160;0x04U</td>
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<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>Max banks in a Zynq GPIO device. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gab8661a0444fd67d2b87a14b3c196e571">&#9670;&nbsp;</a></span>XGPIOPS_MAX_BANKS_ZYNQMP</h2>

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          <td class="memname">#define XGPIOPS_MAX_BANKS_ZYNQMP&#160;&#160;&#160;0x06U</td>
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<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>Max banks in a Zynq Ultrascale+ MP GPIO device. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaff08ac5be0729f046324cae2706aaf9a">&#9670;&nbsp;</a></span>XGpioPs_ReadReg</h2>

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          <td class="memname">#define XGpioPs_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_In32((BaseAddr) + (u32)(RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops__hw_8h.html">xgpiops_hw.h</a>&gt;</code></p>

<p>This macro reads the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddr</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__gpiops__v3__1.html#ga158c9afe847d2b5f6bab24d20926c359">XGpioPs_GetDirection()</a>, <a class="el" href="group__gpiops__v3__1.html#gad1e07837d6bfe1cf16d0b8a454a7de29">XGpioPs_GetIntrType()</a>, <a class="el" href="group__gpiops__v3__1.html#gac182a9828e0ecfdc7a1cbe0c5a1a763f">XGpioPs_GetOutputEnable()</a>, <a class="el" href="group__gpiops__v3__1.html#gaff7a79032f9e298f73c48763e7723bfd">XGpioPs_IntrGetEnabled()</a>, <a class="el" href="group__gpiops__v3__1.html#ga029493370cece06799abb021207cf53f">XGpioPs_IntrGetStatus()</a>, and <a class="el" href="group__gpiops__v3__1.html#ga8e7bc106ec7c6108c26dfe835713d501">XGpioPs_Read()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga3ad586332c0958c5044450d735127337">&#9670;&nbsp;</a></span>XGpioPs_WriteReg</h2>

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          <td class="memname">#define XGpioPs_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops__hw_8h.html">xgpiops_hw.h</a>&gt;</code></p>

<p>This macro writes to the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddr</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the offset of the register to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__gpiops__v3__1.html#ga1168915d3d7b4803bcf30799e0bfdc32">XGpioPs_IntrClear()</a>, <a class="el" href="group__gpiops__v3__1.html#ga5b84f2cbaaa08abf138209b975192326">XGpioPs_IntrDisable()</a>, <a class="el" href="group__gpiops__v3__1.html#ga812e5a4df20dcae1a95ec4b15d36f039">XGpioPs_IntrEnable()</a>, <a class="el" href="group__gpiops__v3__1.html#ga85638e14681720794efa7e55d69360fc">XGpioPs_SetDirection()</a>, <a class="el" href="group__gpiops__v3__1.html#ga47789beb1dcd80b9ef68adaa9eb6b6bf">XGpioPs_SetIntrType()</a>, <a class="el" href="group__gpiops__v3__1.html#ga867a6006d591516ed79727bb6392b9ac">XGpioPs_SetOutputEnable()</a>, and <a class="el" href="group__gpiops__v3__1.html#gacda78d38a3b2dbf4398c5df2c88e0424">XGpioPs_Write()</a>.</p>

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<h2 class="groupheader">Typedef Documentation</h2>
<a id="ga85028e3aa9d71291581c0c7036f6c2d9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga85028e3aa9d71291581c0c7036f6c2d9">&#9670;&nbsp;</a></span>XGpioPs_Handler</h2>

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          <td class="memname">typedef void(* XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status)</td>
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<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This handler data type allows the user to define a callback function to handle the interrupts for the GPIO device. </p>
<p>The application using this driver is expected to define a handler of this type, to support interrupt driven mode. The handler executes in an interrupt context such that minimal processing should be performed.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CallBackRef</td><td>is a callback reference passed in by the upper layer when setting the callback functions for a GPIO bank. It is passed back to the upper layer when the callback is invoked. Its type is not important to the driver component, so it is a void pointer. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank for which the interrupt status has changed. </td></tr>
    <tr><td class="paramname">Status</td><td>is the Interrupt status of the GPIO bank. </td></tr>
  </table>
  </dd>
</dl>

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</div>
<h2 class="groupheader">Function Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#ga33d678e910c69c63487773ca55abff47">&#9670;&nbsp;</a></span>StubHandler()</h2>

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          <td class="memname">void StubHandler </td>
          <td>(</td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallBackRef</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Bank</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Status</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>This is a stub for the status callback. </p>
<p>The stub is here in case the upper layers do not set the handler.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CallBackRef</td><td>is a pointer to the upper layer callback reference </td></tr>
    <tr><td class="paramname">Bank</td><td>is the GPIO Bank in which an interrupt occurred. </td></tr>
    <tr><td class="paramname">Status</td><td>is the Interrupt status of the GPIO bank.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga158c9afe847d2b5f6bab24d20926c359">&#9670;&nbsp;</a></span>XGpioPs_GetDirection()</h2>

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          <td class="memname">u32 XGpioPs_GetDirection </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Get the Direction of the pins of the specified GPIO Bank. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<p>return Returns a 32 bit mask of the Direction register. Bits with 0 are in Input mode, bits with 1 are in Output Mode.</p>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#gaff08ac5be0729f046324cae2706aaf9a">XGpioPs_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga07a1af7cd9070c4037773cc30d53c364">&#9670;&nbsp;</a></span>XGpioPs_GetDirectionPin()</h2>

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          <td class="memname">u32 XGpioPs_GetDirectionPin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Get the Direction of the specified pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number for which the Direction is to be retrieved. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Direction of the specified pin.<ul>
<li>0 for Input Direction</li>
<li>1 for Output Direction</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gad1e07837d6bfe1cf16d0b8a454a7de29">&#9670;&nbsp;</a></span>XGpioPs_GetIntrType()</h2>

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          <td class="memname">void XGpioPs_GetIntrType </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>IntrType</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>IntrPolarity</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32 *&#160;</td>
          <td class="paramname"><em>IntrOnAny</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function is used for getting the Interrupt Type, Interrupt Polarity and Interrupt On Any for the specified GPIO Bank pins. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to an <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">IntrType</td><td>returns the 32 bit mask of the interrupt type. 0 means Level Sensitive and 1 means Edge Sensitive. </td></tr>
    <tr><td class="paramname">IntrPolarity</td><td>returns the 32 bit mask of the interrupt polarity. 0 means Active Low or Falling Edge and 1 means Active High or Rising Edge. </td></tr>
    <tr><td class="paramname">IntrOnAny</td><td>returns the 32 bit mask of the interrupt trigger for edge triggered interrupts. 0 means trigger on single edge using the configured interrupt polarity and 1 means trigger on both edges.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#gaff08ac5be0729f046324cae2706aaf9a">XGpioPs_ReadReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="group__gpiops__v3__1.html#ga173133193aeba362fa0a5c6e7cdd8dfa">XGpioPs_SelfTest()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga1d91233cc0556e3eb8d39cc856b6436c">&#9670;&nbsp;</a></span>XGpioPs_GetIntrTypePin()</h2>

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          <td class="memname">u8 XGpioPs_GetIntrTypePin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function returns the IRQ Type of a given GPIO pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to an <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number whose IRQ type is to be obtained. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Use XGPIOPS_IRQ_TYPE_* defined in <a class="el" href="xgpiops_8h.html">xgpiops.h</a> for the IRQ type returned by this function. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

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<a id="gac182a9828e0ecfdc7a1cbe0c5a1a763f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac182a9828e0ecfdc7a1cbe0c5a1a763f">&#9670;&nbsp;</a></span>XGpioPs_GetOutputEnable()</h2>

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          <td class="memname">u32 XGpioPs_GetOutputEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Get the Output Enable status of the pins of the specified GPIO Bank. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<p>return Returns a a 32 bit mask of the Output Enable register. Bits with 0 are in Disabled state, bits with 1 are in Enabled State.</p>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#gaff08ac5be0729f046324cae2706aaf9a">XGpioPs_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5d3c0e39d48cd827e3e10be5429f5b30">&#9670;&nbsp;</a></span>XGpioPs_GetOutputEnablePin()</h2>

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          <td class="memname">u32 XGpioPs_GetOutputEnablePin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Get the Output Enable status of the specified pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number for which the Output Enable status is to be retrieved. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Output Enable of the specified pin.<ul>
<li>0 if Output Enable is disabled for this pin</li>
<li>1 if Output Enable is enabled for this pin</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga1168915d3d7b4803bcf30799e0bfdc32">&#9670;&nbsp;</a></span>XGpioPs_IntrClear()</h2>

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          <td class="memname">void XGpioPs_IntrClear </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function clears pending interrupt(s) with the provided mask. </p>
<p>This function should be called after the software has serviced the interrupts that are pending.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">Mask</td><td>is the mask of the interrupts to be cleared. Bit positions of 1 will be cleared. Bit positions of 0 will not change the previous interrupt status.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#ga3ad586332c0958c5044450d735127337">XGpioPs_WriteReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="group__gpiops__v3__1.html#gaca8012790789d80573f4b2fa9e601e7c">XGpioPs_IntrHandler()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga27216bebe86f0d32540920a40674340f">&#9670;&nbsp;</a></span>XGpioPs_IntrClearPin()</h2>

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          <td class="memname">void XGpioPs_IntrClearPin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function clears the specified pending interrupt. </p>
<p>This function should be called after the software has serviced the interrupts that are pending.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number for which the interrupt status is to be cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5b84f2cbaaa08abf138209b975192326">&#9670;&nbsp;</a></span>XGpioPs_IntrDisable()</h2>

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          <td class="memname">void XGpioPs_IntrDisable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function disables the interrupts for the specified pins in the specified bank. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">Mask</td><td>is the bit mask of the pins for which interrupts are to be disabled. Bit positions of 1 will be disabled. Bit positions of 0 will keep the previous setting.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#ga3ad586332c0958c5044450d735127337">XGpioPs_WriteReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="group__gpiops__v3__1.html#ga173133193aeba362fa0a5c6e7cdd8dfa">XGpioPs_SelfTest()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga8a00fd131bf76eab2dcdd48079845b37">&#9670;&nbsp;</a></span>XGpioPs_IntrDisablePin()</h2>

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          <td class="memname">void XGpioPs_IntrDisablePin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function disables the interrupts for the specified pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number for which the interrupt is to be disabled. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga812e5a4df20dcae1a95ec4b15d36f039">&#9670;&nbsp;</a></span>XGpioPs_IntrEnable()</h2>

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          <td class="memname">void XGpioPs_IntrEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function enables the interrupts for the specified pins in the specified bank. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">Mask</td><td>is the bit mask of the pins for which interrupts are to be enabled. Bit positions of 1 will be enabled. Bit positions of 0 will keep the previous setting.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#ga3ad586332c0958c5044450d735127337">XGpioPs_WriteReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="group__gpiops__v3__1.html#ga173133193aeba362fa0a5c6e7cdd8dfa">XGpioPs_SelfTest()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gadc4ea201a1c488a1b667a77f3c6fd23b">&#9670;&nbsp;</a></span>XGpioPs_IntrEnablePin()</h2>

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          <td class="memname">void XGpioPs_IntrEnablePin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function enables the interrupt for the specified pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number for which the interrupt is to be enabled. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaff7a79032f9e298f73c48763e7723bfd">&#9670;&nbsp;</a></span>XGpioPs_IntrGetEnabled()</h2>

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          <td class="memname">u32 XGpioPs_IntrGetEnabled </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function returns the interrupt enable status for a bank. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Enabled interrupt(s) in a 32-bit format. Bit positions with 1 indicate that the interrupt for that pin is enabled, bit positions with 0 indicate that the interrupt for that pin is disabled.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#gaff08ac5be0729f046324cae2706aaf9a">XGpioPs_ReadReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="group__gpiops__v3__1.html#gaca8012790789d80573f4b2fa9e601e7c">XGpioPs_IntrHandler()</a>, and <a class="el" href="group__gpiops__v3__1.html#ga173133193aeba362fa0a5c6e7cdd8dfa">XGpioPs_SelfTest()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga612ecefd5e1f81cccf6b878505b7e242">&#9670;&nbsp;</a></span>XGpioPs_IntrGetEnabledPin()</h2>

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          <td class="memname">u32 XGpioPs_IntrGetEnabledPin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function returns whether interrupts are enabled for the specified pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number for which the interrupt enable status is to be known. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE if the interrupt is enabled.</li>
<li>FALSE if the interrupt is disabled.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga029493370cece06799abb021207cf53f">&#9670;&nbsp;</a></span>XGpioPs_IntrGetStatus()</h2>

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          <td class="memname">u32 XGpioPs_IntrGetStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function returns interrupt status read from Interrupt Status Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The value read from Interrupt Status Register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#gaff08ac5be0729f046324cae2706aaf9a">XGpioPs_ReadReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="group__gpiops__v3__1.html#gaca8012790789d80573f4b2fa9e601e7c">XGpioPs_IntrHandler()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga7ed8ee94fdf3f26e765a997aeab64595">&#9670;&nbsp;</a></span>XGpioPs_IntrGetStatusPin()</h2>

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          <td class="memname">u32 XGpioPs_IntrGetStatusPin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function returns interrupt enable status of the specified pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number for which the interrupt enable status is to be known. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE if the interrupt has occurred.</li>
<li>FALSE if the interrupt has not occurred.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaca8012790789d80573f4b2fa9e601e7c">&#9670;&nbsp;</a></span>XGpioPs_IntrHandler()</h2>

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          <td class="memname">void XGpioPs_IntrHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function is the interrupt handler for GPIO interrupts.It checks the interrupt status registers of all the banks to determine the actual bank in which an interrupt has been triggered. </p>
<p>It then calls the upper layer callback handler set by the function XGpioPs_SetBankHandler(). The callback is called when an interrupt</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function does not save and restore the processor context such that the user must provide this processing. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#aca8b8269a2bd384f19de77e312de684a">XGpioPs::Handler</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, <a class="el" href="struct_x_gpio_ps.html#aea00d5eac94a0ae4b17d3ec0061afba1">XGpioPs::MaxBanks</a>, <a class="el" href="group__gpiops__v3__1.html#ga1168915d3d7b4803bcf30799e0bfdc32">XGpioPs_IntrClear()</a>, <a class="el" href="group__gpiops__v3__1.html#gaff7a79032f9e298f73c48763e7723bfd">XGpioPs_IntrGetEnabled()</a>, and <a class="el" href="group__gpiops__v3__1.html#ga029493370cece06799abb021207cf53f">XGpioPs_IntrGetStatus()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga9c49687af4625a0ed49f376d3ff1b045">&#9670;&nbsp;</a></span>XGpioPs_LookupConfig()</h2>

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          <td class="memname"><a class="el" href="struct_x_gpio_ps___config.html">XGpioPs_Config</a> * XGpioPs_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
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<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function looks for the device configuration based on the unique device ID. </p>
<p>The table XGpioPs_ConfigTable[] contains the configuration information for each device in the system.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique device ID of the device being looked up.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga8e7bc106ec7c6108c26dfe835713d501">&#9670;&nbsp;</a></span>XGpioPs_Read()</h2>

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          <td class="memname">u32 XGpioPs_Read </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Read the Data register of the specified GPIO bank. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Current value of the Data register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is used for reading the state of all the GPIO pins of specified bank. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#gaff08ac5be0729f046324cae2706aaf9a">XGpioPs_ReadReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga13b3e68acd59636ebaed5c71055e583c">&#9670;&nbsp;</a></span>XGpioPs_ReadPin()</h2>

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          <td class="memname">u32 XGpioPs_ReadPin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Read Data from the specified pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number for which the data has to be read. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. See <a class="el" href="xgpiops_8h.html">xgpiops.h</a> for the mapping of the pin numbers in the banks.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Current value of the Pin (0 or 1).</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is used for reading the state of the specified GPIO pin. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga173133193aeba362fa0a5c6e7cdd8dfa">&#9670;&nbsp;</a></span>XGpioPs_SelfTest()</h2>

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          <td class="memname">s32 XGpioPs_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function runs a self-test on the GPIO driver/device. </p>
<p>This function does a register read/write test on some of the Interrupt Registers.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the self-test passed.<ul>
<li>XST_FAILURE otherwise. </li>
</ul>
</li>
</ul>
</dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, <a class="el" href="group__gpiops__v3__1.html#gac5c6fe277747f034cd30c3f3e770dc5b">XGPIOPS_BANK0</a>, <a class="el" href="group__gpiops__v3__1.html#gad1e07837d6bfe1cf16d0b8a454a7de29">XGpioPs_GetIntrType()</a>, <a class="el" href="group__gpiops__v3__1.html#ga5b84f2cbaaa08abf138209b975192326">XGpioPs_IntrDisable()</a>, <a class="el" href="group__gpiops__v3__1.html#ga812e5a4df20dcae1a95ec4b15d36f039">XGpioPs_IntrEnable()</a>, <a class="el" href="group__gpiops__v3__1.html#gaff7a79032f9e298f73c48763e7723bfd">XGpioPs_IntrGetEnabled()</a>, and <a class="el" href="group__gpiops__v3__1.html#ga47789beb1dcd80b9ef68adaa9eb6b6bf">XGpioPs_SetIntrType()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#gacd63e0e5c7ed18517d54104e4ad6dcd4">&#9670;&nbsp;</a></span>XGpioPs_SetCallbackHandler()</h2>

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          <td class="memname">void XGpioPs_SetCallbackHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallBackRef</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__gpiops__v3__1.html#ga85028e3aa9d71291581c0c7036f6c2d9">XGpioPs_Handler</a>&#160;</td>
          <td class="paramname"><em>FuncPointer</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function sets the status callback function. </p>
<p>The callback function is called by the XGpioPs_IntrHandler when an interrupt occurs.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">CallBackRef</td><td>is the upper layer callback reference passed back when the callback function is invoked. </td></tr>
    <tr><td class="paramname">FuncPtr</td><td>is the pointer to the callback function.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a7bb5325d472614845866cb7abf370ce9">XGpioPs::CallBackRef</a>, <a class="el" href="struct_x_gpio_ps.html#aca8b8269a2bd384f19de77e312de684a">XGpioPs::Handler</a>, and <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga85638e14681720794efa7e55d69360fc">&#9670;&nbsp;</a></span>XGpioPs_SetDirection()</h2>

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          <td class="memname">void XGpioPs_SetDirection </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Direction</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Set the Direction of the pins of the specified GPIO Bank. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">Direction</td><td>is the 32 bit mask of the Pin direction to be set for all the pins in the Bank. Bits with 0 are set to Input mode, bits with 1 are set to Output Mode.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is used for setting the direction of all the pins in the specified bank. The previous state of the pins is not maintained. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#ga3ad586332c0958c5044450d735127337">XGpioPs_WriteReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2dc5d53b864a3beb90481390f06e1099">&#9670;&nbsp;</a></span>XGpioPs_SetDirectionPin()</h2>

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          <td class="memname">void XGpioPs_SetDirectionPin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Direction</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Set the Direction of the specified pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number to which the Data is to be written. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">Direction</td><td>is the direction to be set for the specified pin. Valid values are 0 for Input Direction, 1 for Output Direction.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

</div>
</div>
<a id="ga47789beb1dcd80b9ef68adaa9eb6b6bf"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga47789beb1dcd80b9ef68adaa9eb6b6bf">&#9670;&nbsp;</a></span>XGpioPs_SetIntrType()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XGpioPs_SetIntrType </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>IntrType</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>IntrPolarity</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>IntrOnAny</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function is used for setting the Interrupt Type, Interrupt Polarity and Interrupt On Any for the specified GPIO Bank pins. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to an <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">IntrType</td><td>is the 32 bit mask of the interrupt type. 0 means Level Sensitive and 1 means Edge Sensitive. </td></tr>
    <tr><td class="paramname">IntrPolarity</td><td>is the 32 bit mask of the interrupt polarity. 0 means Active Low or Falling Edge and 1 means Active High or Rising Edge. </td></tr>
    <tr><td class="paramname">IntrOnAny</td><td>is the 32 bit mask of the interrupt trigger for edge triggered interrupts. 0 means trigger on single edge using the configured interrupt polarity and 1 means trigger on both edges.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is used for setting the interrupt related properties of all the pins in the specified bank. The previous state of the pins is not maintained. To change the Interrupt properties of a single GPIO pin, use the function XGpioPs_SetPinIntrType(). </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#ga3ad586332c0958c5044450d735127337">XGpioPs_WriteReg</a>.</p>

<p class="reference">Referenced by <a class="el" href="group__gpiops__v3__1.html#ga173133193aeba362fa0a5c6e7cdd8dfa">XGpioPs_SelfTest()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga963415d9096b5887c5388cea74cd1116">&#9670;&nbsp;</a></span>XGpioPs_SetIntrTypePin()</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XGpioPs_SetIntrTypePin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>IrqType</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8h.html">xgpiops.h</a>&gt;</code></p>

<p>This function is used for setting the IRQ Type of a single GPIO pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to an <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number whose IRQ type is to be set. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">IrqType</td><td>is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_* defined in <a class="el" href="xgpiops_8h.html">xgpiops.h</a> to specify the IRQ type.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
<p>&lt; Default statement is added for MISRA C compliance. </p>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#ga84b599940b75f6e1d6920c7b33fc2789">XGPIOPS_IRQ_TYPE_LEVEL_LOW</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga867a6006d591516ed79727bb6392b9ac">&#9670;&nbsp;</a></span>XGpioPs_SetOutputEnable()</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XGpioPs_SetOutputEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>OpEnable</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Set the Output Enable of the pins of the specified GPIO Bank. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">OpEnable</td><td>is the 32 bit mask of the Output Enables to be set for all the pins in the Bank. The Output Enable of bits with 0 are disabled, the Output Enable of bits with 1 are enabled.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is used for setting the Output Enables of all the pins in the specified bank. The previous state of the Output Enables is not maintained. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#ga3ad586332c0958c5044450d735127337">XGpioPs_WriteReg</a>.</p>

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<a id="gae84916ec202e4d3a8a46a20857753eec"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae84916ec202e4d3a8a46a20857753eec">&#9670;&nbsp;</a></span>XGpioPs_SetOutputEnablePin()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XGpioPs_SetOutputEnablePin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>OpEnable</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Set the Output Enable of the specified pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number to which the Data is to be written. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">OpEnable</td><td>specifies whether the Output Enable for the specified pin should be enabled. Valid values are 0 for Disabling Output Enable, 1 for Enabling Output Enable.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

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<a id="gacda78d38a3b2dbf4398c5df2c88e0424"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gacda78d38a3b2dbf4398c5df2c88e0424">&#9670;&nbsp;</a></span>XGpioPs_Write()</h2>

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      <table class="memname">
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          <td class="memname">void XGpioPs_Write </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Bank</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Write to the Data register of the specified GPIO bank. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Bank</td><td>is the bank number of the GPIO to operate on. Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">Data</td><td>is the value to be written to the Data register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function is used for writing to all the GPIO pins of the bank. The previous state of the pins is not maintained. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps___config.html#af6895118cd185deea6b71ff3b67c65da">XGpioPs_Config::BaseAddr</a>, <a class="el" href="struct_x_gpio_ps.html#a312cec02e6e2550ba15824fad0596921">XGpioPs::GpioConfig</a>, <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>, and <a class="el" href="group__gpiops__v3__1.html#ga3ad586332c0958c5044450d735127337">XGpioPs_WriteReg</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga4f1789ef303dcbfbdb402663e7b0019d">&#9670;&nbsp;</a></span>XGpioPs_WritePin()</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XGpioPs_WritePin </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_gpio_ps.html">XGpioPs</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Pin</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops_8c.html">xgpiops.c</a>&gt;</code></p>

<p>Write data to the specified pin. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_gpio_ps.html" title="The XGpioPs driver instance data. ">XGpioPs</a> instance. </td></tr>
    <tr><td class="paramname">Pin</td><td>is the pin number to which the Data is to be written. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. </td></tr>
    <tr><td class="paramname">Data</td><td>is the data to be written to the specified pin (0 or 1).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function does a masked write to the specified pin of the specified GPIO bank. The previous state of other pins is maintained. </dd></dl>

<p class="reference">References <a class="el" href="struct_x_gpio_ps.html#a3acad7612d69a3b801cea87a78aaa60b">XGpioPs::IsReady</a>.</p>

</div>
</div>
<h2 class="groupheader">Variable Documentation</h2>
<a id="gadfc4a76613b301ad3af6d2014505e745"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadfc4a76613b301ad3af6d2014505e745">&#9670;&nbsp;</a></span>XGpioPs_ConfigTable <span class="overload">[1/2]</span></h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname"><a class="el" href="struct_x_gpio_ps___config.html">XGpioPs_Config</a> XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES]</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops__sinit_8c.html">xgpiops_sinit.c</a>&gt;</code></p>

<p>This table contains configuration information for each GPIO device in the system. </p>

</div>
</div>
<a id="gadfc4a76613b301ad3af6d2014505e745"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadfc4a76613b301ad3af6d2014505e745">&#9670;&nbsp;</a></span>XGpioPs_ConfigTable <span class="overload">[2/2]</span></h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname"><a class="el" href="struct_x_gpio_ps___config.html">XGpioPs_Config</a> XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES]</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xgpiops__g_8c.html">xgpiops_g.c</a>&gt;</code></p>
<b>Initial value:</b><div class="fragment"><div class="line">= {</div><div class="line">        {</div><div class="line">                (u16)XPAR_XGPIOPS_0_DEVICE_ID,  </div><div class="line">                (u32)XPAR_XGPIOPS_0_BASEADDR            </div><div class="line">        }</div><div class="line">}</div></div><!-- fragment -->
<p>This table contains configuration information for each GPIO device in the system. </p>

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